The invention relates in general to interconnect systems for providing signal paths between an integrated circuit (IC) tester and pads on the surfaces of ICs, and in particular to a system for distributing a single test signal output of an IC tester to multiple pads on one or more ICs.
An integrated circuit (IC) manufacturer fabricates an array of similar integrated circuits on a semiconductor wafer and then cuts the wafer to separate the ICs from one another. The ICs include pads on their upper surfaces providing points of contact for signal paths conveying IC output signals to other circuits or for receiving IC input signals from other circuits. The manufacturer may mount an IC in a package using bond wires to link the pads on the surface of the IC to package pins providing signal paths to external circuits. An IC can also be mounted directly on a printed circuit board (PCB) either by soldering pads on its surface to correspondingly arranged contact pads on the surfaces of the PCB or by providing spring contacts between pads on the surface of the ICs and the PCB""s contact pads. The spring contacts may be attached to the IC""s input/output (I/O) pads on the IC with their tips contacting the PCB""s pads, may be attached to the PCB""s pads with their tips contacting the IC""s I/O pads, or may be attached to both the IC and PCB pads.
ICs are often tested at the wafer level before they are separated from one another. For example, as illustrated in FIG. 1, an IC tester 10 for testing ICs 12 residing on a wafer 14 includes a set of tester channels, each of which may either transmit a test signal to an IC I/O pad or monitor an IC output signal appearing at an IC I/O pad to determine whether the IC responds correctly to its input signals. A bundle of coaxial cables 18 provides separate signal paths between the input/output terminal of each tester channel and a cable connector 16 on a probe board assembly 20. A set of probes 22 connects pads on the lower surface of probe board assembly 20 to the pads on the upper surfaces of ICs 12. While coaxial or other kinds of cables 18 have been used to link a tester 10 to a probe board assembly 20 as illustrated in FIG. 1, pogo pin connectors have also often been used to provide signals paths between an IC tester and a probe board assembly.
Various types of structures can be used to implement probes 22 including, for example, wire bond and lithographic spring contacts, needle probes, and cobra probes. When spring contacts are employed to implement probes 22, they can be formed on the I/O pads of ICs 12 when probe board assembly 20 includes pads on its lower surface arranged to contact the tips of the spring contacts. U.S. Pat. No. 6,064,213, issued May 16, 2000 to Khandros et al (incorporated herein by reference), exemplifies such a probe board assembly.
When spring contacts are not formed on the I/O pads of ICs 12, they can be formed on the lower surface of probe board assembly 20 and arranged so that their tips contact the I/O pads of ICs 12. U.S. Pat. No. 5,974,662 issued Nov. 2, 1999 to Eldridge et al (incorporated herein by reference) describes an example of a probe board assembly employing spring contact probes. The following documents (also incorporated herein by reference) disclose various exemplary methods for manufacturing spring contacts: U.S. Pat. No. 6,336,269 issued Jan. 8, 2002, to Eldridge et al., U.S. Pat. No. 6,255,126 issued Jul. 31, 2001 to Mathieu et al., U.S. patent application Ser. No. 09/710,539 filed Nov. 9, 2000, and U.S. patent application Ser. No. 09/746,716 filed Dec. 22, 2000.
Probe board assembly 20 provides signal paths between cable connectors 16 and the pads on the lower surface of probe board assembly 20 that probes 22 contact. Some probe board assemblies 20 are formed by multiple-layer printed circuit board having traces formed on the various layers for conveying signals horizontally and vias for conveying signals vertically though the layers. Other probe board assemblies include several separate substrate layers interconnected through spring contacts. See for example, U.S. Pat. No. 5,974,662 issued Nov. 2, 1992 to Eldridge, et al, incorporated herein by reference.
To test all ICs 12 on wafer 14, the channels within tester 10 must be able to access all I/O pads of all ICs. For example, ICs 12 might be random access memories (RAMs), with each RAM having eight I/O pads acting as an 8-bit address input, another eight I/O pads acting as an 8-bit data input/output, and one or more additional I/O pads for receiving input control signals. To test such a RAM IC, tester 10 writes data to each of its addresses, reads the data back out of each address and determines whether the data read out of the RAM matches the data written into it.
Thus tester 10 might include seventeen or more channels for each RAM IC to be tested, including eight channels for supplying signals conveying the 8-bit address, eight bi-directional channels for transmitting and receiving the 8-bit data, and one or more additional channels for providing the RAM""s control signal inputs. However since a wafer 14 typically includes a large number of ICs 12, tester 10 would require a very large number of channels to concurrently test all of the ICs. Thus wafer-level IC testers typically test only a portion of the ICs of a wafer at a time, with the wafer being repositioned under the probes after each group of ICs is tested so that a next group of ICs can be tested.
What is needed is an inexpensive interconnect system that can distribute a test signal from an IC tester to pads of several ICs at the same time without causing substantial distortion due to signal reflection, and without requiring transmission lines having more than one characteristic impedance.
The invention relates to an interconnect system for providing signal paths between an integrated circuit (IC) tester and input/output (I/O) pads of ICs formed on a semiconductor wafer so that the IC tester can test the ICs. The interconnect system includes a set of probes for accessing the I/O pads and a probe board assembly providing signal paths for conducting signals between the IC tester and the probes.
In accordance with an embodiment of the invention, a branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Isolation resistors within the branching signal path resistively isolate the probes from one another with sufficient resistance that a fault at any IC terminal connecting that IC terminal to a potential source through a low impedance path will not affect the logic state of the test signal arriving at any other IC terminal.
The isolation resistors are also sized relative to characteristic impedances of signal paths in which they reside so as to substantially minimize test signal reflections at the branch points. For example a set of four 200 Ohm isolation resistors are provided at a branch node between a 50 Ohm incoming transmission line and a set of four outgoing transmission lines since the parallel combination of four 200 Ohm resistors provides an equivalent 50 Ohm impedance matching the impedance of the incoming transmission line.
An impedance mismatch can occur between each isolation resistor and the outgoing signal path to which it is linked, as for example when each 200 Ohm isolation resistor is connected to a 50 Ohm outgoing transmission line. Such an impedance mismatch causes the junction between each isolation resistor and an outgoing transmission line to reflect a portion of the test signal as it travels toward a probe. However the isolation resistors are sufficiently large to attenuate such reflections so that they do not substantially distort the test signal upstream of the isolation resistors. Thus a reflection of a test signal in any one branch of the path adds little distortion to the test signal passing into any other branch of that path.
The claims appended to this specification particularly point out and distinctly claim the subject matter of the invention. However those skilled in the art will best understand both the organization and method of operation of what the applicant(s) consider to be the best mode(s) of practicing the invention, together with further advantages and objects of the invention, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.